This invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device for a MOS type logic circuit, wherein said logic circuit can be accelerated in operation.
The high density and highly accelerated operation of integrated circuits are now a matter of the greatest concern in the industry of integrated circuit devices.
This invention aims at improvement of the switching property of integrated circuits by designing the arrangement of said circuits and the patterns defined thereon.
A flip-flop circuit using insulated gate type field effect transistors generally includes various forms. For instance, a flip-flop circuit adopted for large scale integration includes a master-slave type J-K flip-flop circuit system including an AND-NOR flip-flop circuit having such arrangement as shown in FIG. 1.
The master-slave type J-K flip-flop circuit system comprises two AND-NOR flip-flop circuits, each of which is used as a master guide or a slave gate, thereby ensuring reliable data transmission and toggle action, independently of the length of time required for the rise or fall of a clock pulse or a length of time consumed before the termination of the whole clock pulse.
A plurality of flip-flop circuits each arranged as shown in FIG. 1 are practically integrated with high density on a one-chip semiconductor substrate. However, these flip-flop circuits are subject to limitations particularly in respect of the switching speed due to the specific arrangement of an integrated circuit device itself.
The aforesaid AND-NOR flip-flop circuit 11 is arranged as shown in FIGS. 2 and 3. The transistors (1), (2), (3), (4), (5), (6), (8), (10) respectively have diffused source and drain regions and wiring made of, for example, aluminium. These components jointly provide a junction capacitance and floating capacitance. Therefore, a time constant .tau.=CR (a product of capacitance by resistance) is unavoidably defined by said junction capacitance and floating capacitance. With the AND-NOR flip-flop circuits 11, the above-mentioned junction capacities and floating capacities are collectively expressed as C.sub.a, C.sub.b2, C.sub.c2, C.sub.P, C.sub.N.
This invention has been accomplished in view of the above-described drawbacks, and is intended to provide a semiconductor integrated circuit device in which the aforesaid stray capacities are reduced to ensure high speed operation. The arrangement of a semiconductor integrated circuit device allowing for high speed operation has been realized from the arrangement of FIG. 4 which has been defined by analyzing the arrangement of the prior art AND-NOR flip-flop circuit 11.
There will now be described the results of said analysis. With the prior art AND-NOR flip-flop circuit 11. The time constant .tau.=CR in question exerts its effect on the rise of a clock pulse. Referring to FIG. 2, since Preset signal has a low level "L", a clock pulse rises when an N channel transistor 4 is rendered nonconducting and a P channel transistor 10 is rendered conducting, and since a Q.sub.M signal has a low level "L", when an N channel transistor 2 is rendered nonconducting, and a P channel transistor 6 is rendered conducting. Further since a CLOCK signal has a fully high level "H" as viewed from the rising characteristic of the clock pulse, the clock pulse rises when a Q.sub.S output signal from the flip-flop circuit has its level shifted from "H" to "L", while an N channel transistor 1 is rendered conducting and a P channel transistor 5 is rendered nonconducting. Where the Q.sub.S signal has its level changed from "H" to "L", then an N channel transistor 3 is rendered nonconducting, and a P channel transistor 8 is rendered conducting. Therefore, the output terminal of the arrangement of FIG. 4 produces an output signal Q.sub.S ("L".fwdarw."H") having an optional rising time. With the flip-flop circuit of FIG. 2, therefore, the transistors 6, 8, 10 are considered to be associated with the rising property of a clock pulse. Consequently, the stray capacities C.sub.b2, C.sub.c2, C.sub.P, C.sub.N may be regarded as affecting the rising property of a clock pulse. Thus, FIG. 4 may be taken to represent an improved arrangement derived from the analysis of the prior art flip-flop circuit.
Referring to FIG. 4, a voltage impressed between the electrodes of the respective transistors may be expressed as follows: